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ST92R195B
ROMLESS HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
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Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes 0C to +70C Operating Temperature Range available Up to 24 MHz Operation @ 5V10% Minimum instruction cycle time: 375ns at 16 MHz internal clock 4 Mbytes address space 256 Bytes RAM of Register file (accumulators or index registers) 1024 Bytes of on-chip static RAM 8K Bytes of TDSRAM (Teletext and Display Storage RAM) 80-lead QFP package 23 fully programmable I/O pins Serial Peripheral Interface Flexible Clock controller for OSD, Data Slicer and Core clocks running from one single low frequency external crystal. Enhanced Display Controller with 26 rows of 40/80 characters - Serial and Parallel attributes - 10x10 dot Matrix, 512 ROM characters, definable by user - 4/3 and 16/9 supported in 50/60Hz and 100/ 120 Hz mode - Rounding, fringe, double width, double height, scrolling, cursor, full background color, halfintensity color, translucency and half-tone modes Teletext unit, including Data slicer, Acquisition Unit and 8 Kbytes TDSRAM for Data Storage VPS and Wide Screen Signalling slicer Integrated Sync Extractor and Sync Controller 14-bit Voltage Synthesis for tuning reference voltage Up to 8 External Interrupts plus 1 non-maskable interrupt
QFP80
8 x 8-bit programmable PWM outputs with 5V open-drain or push-pull capability s 16-bit Watchdog timer with 8-bit prescaler s One 16-bit standard timer with 8-bit prescaler s 4-channel Analog-to-Digital converter; 5-bit guaranteed s Rich instruction set and 14-Addressing modes Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with RealTime Operating System available from third parties
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Device Summary
Device ST92R195B9 Program Memory ROMLESS TDS VPS/ RAM WSS 8K Yes Package PQFP80
Rev. 2.2
January 2000 1/18
1
ST92R195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST92R195B microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The ST92R195B MCU supports low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File and the Interrupt controller. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. Two basic addressable spaces are available: the Memory space and the Register File, which includes the control and status registers of the onchip peripherals. 1.1.2 Power Saving Modes To optimize performance versus power consumption, a range of operating modes can be dynamically selected. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequency programmable via the CCU. In this mode, the power consumption of the device can be reduced by more than 95% (LP WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode. 1.1.3 I/O Ports Up to 23 I/O lines are dedicated to digital Input/ Output. These lines are grouped into up to five I/O Ports and can be configured on a bit basis under software control to provide timing, status signals, timer and output, analog inputs, external interrupts and serial or parallel I/O. 1.1.4 TV Peripherals A set of on-chip peripherals form a complete system for TV set and VCR applications: - Voltage Synthesis - VPS/WSS Slicer - Teletext Slicer - Teletext Display RAM - OSD 1.1.5 On Screen Display The human interface is provided by the On Screen Display module, this can produce up to 26 lines of up to 80 characters from a ROM defined 512 character set. The character resolution is 10x10 dots. Four character sizes are supported. Serial attributes allow the user to select foreground and background colours, character size and fringe background. Parallel attributes can be used to select additional foreground and background colors and underline on a character by character basis. 1.1.6 Teletext and Display RAM The internal 8k Teletext and Display storage RAM can be used to store Teletext pages as well as Display parameters.
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ST92R195B - GENERAL DESCRIPTION
INTRODUCTION (Cont'd) 1.1.7 Teletext, VPS and WSS Data Slicers The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS and WSS information from the video signal. Hardware Hamming decoding is provided. 1.1.8 Voltage Synthesis Tuning Control 14-bit Voltage Synthesis using the PWM (Pulse Width Modulation)/BRM (Bit Rate Modulation) technique can be used to generate tuning voltages for TV set applications. The tuning voltage is output on one of two separate output pins. 1.1.9 PWM Output Control of TV settings is able to be made with up to eight 8-bit PWM outputs, with a frequency maximum of 23,437Hz at 8-bit resolution (INTCLK = 12 MHz). Low resolutions with higher frequency operation can be programmed.
1.1.10 Serial Peripheral Interface (SPI) The SPI bus is used to communicate with external devices via the SPI, or I C bus communication standards. The SPI uses a single line for data input and output. A second line is used for a synchronous clock signal. 1.1.11 Standard Timer (STIM) The ST92R195B has one Standard Timer that includes a programmable 16-bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes. 1.1.12 Analog/Digital Converter (ADC) In addition there is a 4 channel Analog to Digital Converter with integral sample and hold, fast 5.75s conversion time and 6-bit guaranteed resolution.
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ST92R195B - GENERAL DESCRIPTION
Figure 1. ST92R195B Block Diagram
ADDR[15:0] DAT[7:0] ASN RWN DSN MMU[5:0] External Memory I/F 1 Kbyte RAM I/O PORT 0
3
P0[2:0]
I/O PORT 2 I/O PORT 3 I/O PORT 4
6
P2[5:0]
8 Kbytes TDSRAM TRI
4
P3[7:4]
MEMORY BUS
256 bytes Register File 8/16-bit CPU MMU
8
P4[7:0]
I/O PORT 5 DATA SLICER & ACQUISITIO N UNIT SYNC. EXTRACTION REGISTER BUS VPS/WSS DATA SLICER ADC
2
P5[1:0]
NMI INT[7:0]
Interrupt Management ST9+ CORE
TXCF CVBS1
OSCIN OSCOUT RESET RESETO
RCCU 16-BIT TIMER/ WATCHDOG
WSCR WSCF CVBS2
SDO/SDI SCK
SPI
AIN[4:1] EXTRG
VSYNC HSYNC/CSYNC CSO FREQ. PXFM MULTIP. R/G/B/FB TSLU HT
MCFM
TIMING AND CLOCK CTRL
SYNC CONTROL ON SCREEN DISPLAY PWM D/A CONVERTER
STOUT
STANDARD TIMER VOLTAGE SYNTHESIS
VSO[2:1]
PWM[7:0]
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
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ST92R195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION ADDR[15:0] External memory interface address bus. CVBS1 Composite video input signal for the Teletext slicer and sync extraction. CVBS2 Composite video input signal for the VPS/ WSS slicer. Pin AC coupled. CVBSO, JTDO, JTCK Test pins: leave floating. DAT[7:0] External memory interface data bus. DSN Data strobe for external memory interface. FB Fast Blanking. Video analog DAC output. GND Digital circuit ground. GNDA Analog circuit ground (must be tied externally to digital GND). GNDM External memory interface ground. HSYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to OSD. Positive or negative polarity. JTRST0 Test pin: must be tied to GND. MCFM Analog pin for the display pixel frequency multiplier. MMU[5:0] External memory interface MMU segment bus OSCIN, OSCOUT Oscillator (input and output). These pins connect a parallel-resonant crystal (24MHz maximum), or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator inverter. PXFM Analog pin for the Display Pixel Frequency Multiplier RESET Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. R/G/B Red/Green/Blue. Video color analog DAC outputs. RWN Read/Write strobe for external memory interface. TEST0 Test pin: must be tied to VDDA. TXCF Analog pin for the teletext PLL. VDD Main power supply voltage (5V 10%, digital) VDDA Analog power supply (must be tied externally to VDDA ). VDDM External memory interface power supply. VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity. WSCF, WSCR Analog pins for the VPS/WPP slicer. These pins must be tied to ground or not connected. P0[2:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]- I/O Port Lines (Input/Output, TTL or CMOS compatible). 23 lines grouped into I/O ports, bit programmable as general purpose I/O or as Alternate functions (see I/O section). Important: Note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 I/O Port Alternate Functions. Each pin of the I/O ports of the ST92R195B may assume software programmable Alternate Functions as shown in the Pin Configuration drawings. Table 1. shows the Functions allocated to each I/O Port pin.
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ST92R195B - GENERAL DESCRIPTION
Figure 2. 80-Pin Package Pin-Out
ADDR15 ADDR12 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DAT0 DAT1 DAT2 DAT7 DAT6 DAT5
MMU0 MMU3 ADDR10 DSN ADDR11 ADDR9 ADDR8 RWN GNDM VDDM OSCIN OSCOUT ADDR13 ADDR14 MMU1 MMU2 MMU4 MMU5 CSO/RESETO/P3.7 ASN/P3.6 P3.5 P3.4 SDI/SDO/INT1/P5.1 SCK/INT2/P5.0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 63 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
DAT4 DAT3 GNDA CVBS1 CVBS2 TEST0 CVBSO TXCF JTRST0 MCFM RESET PXFM VDDA WSCF WSCR HSYNC/CSYNC VSYNC R G B FB P4.0/PWM0 P4.1/PWM1 P4.2/PWM2
42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PWM7/EXTRG/INT3/STOUT/P4.7 P0.1 P0.0 VDD AIN4/P0.2 INT7/P2.0 NMI/P2.4 GND PWM6/P4.6 PWM5/P4.5 INT5/AIN1/P2.1 INT6/VSO1/P2.3 INT0/AIN2/P2.2 INT4/AIN3/VSO2/P2.5 PWM4/P4.4 PWM3/TSLU/HT/P4.3
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ST92R195B - GENERAL DESCRIPTION
Table 1. ST92R195B I/O Port Alternate Function
Port Name P0.0 P0.1 P0.2 P2.0 P2.1 General Purpose I/O Pin No. PQFP80 30 29 28 25 36 AIN4 INT7 AIN1 INT5 INT0 AIN2 INT6 VSO1 NMI AIN3 P2.5 38 INT4 VSO2 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 22 21 All ports useable 20 for general purpose I/O (input, 19 output or bidirectional) 43 42 41 Alternate Functions I/O I/O I I I I I I I O I I I O I/O I/O ASN RESET0 CSO PWM0 PWM1 PWM2 PWM3 P4.3 40 TSLU HT P4.4 P4.5 P4.6 39 33 32 PWM4 PWM5 PWM6 EXTRG P4.7 31 PWM7 STOUT INT3 P5.0 24 INT2 SCK SDO P5.1 23 SDI INT1 O O O O O O O O O O O O I O O I I O O I I External Memory Interface Address Strobe Internal Reset Output Composite Sync output PWM Output 0 PWM Output 1 PWM Output 2 PWM Output 3 Translucency Digital Output Half-tone Output PWM Output 4 PWM Output 5 PWM Output 6 A/D Converter External Trigger Input PWM Output 7 Standard Timer Output External Interrupt 3 External Interrupt 2 SPI Serial Clock SPI Serial Data Out SPI Serial Data In External Interrupt 1 A/D Analog Data Input 4 External Interrupt 7 A/D Analog Data Input 1 External Interrupt 5 External Interrupt 0 A/D Analog Data Input 2 External Interrupt 6 Voltage Synthesis Output 1 Non Maskable Interrupt Input A/D Analog Data Input 3 External Interrupt 4 Voltage Synthesis Output 2
P2.2
37
P2.3 P2.4
26 27
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ST92R195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) 1.2.2 I/O Port Styles
Pins P0[2:0] P2[5,4,3,2] P2[1:0] P3.7 P3[6,5,4] P4[7:0] P5[1:0] Physical Pull-Up no no no yes no no no Pin Style standard I/O standard I/O std I/O, trigger standard I/O standard I/O standard I/O standard I/O Reset Values BID / OD / TTL BID / OD / TTL BID / OD / TTL AF / PP / TTL BID / OD / TTL BID / OD / TTL BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table To configure the I/O ports, use the information in this table and the Port Bit Configuration Table in the I/O Ports Chapter of the datasheet. Port Style= the hardware characteristics fixed for each port line. Inputs: - If port style = Standard I/O, either TTL or CMOS input level can be selected by software. - If port style = Schmitt trigger, selecting CMOS or TTL input by software has no effect, the input will always be Schmitt Trigger. Weak Pull-Up = This column indicates if a weak pull-up is present or not. - If WPU = yes, then the WPU can be enabled/disable by software - If WPU = no, then enabling the WPU by software has no effect Alternate Functions (AF) = More than one AF cannot be assigned to an external pin at the same time: An alternate function can be selected as follows. AF Inputs: - AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC analog inputs which must be explicitly selected as AF by software.
AF Outputs or Bidirectional Lines: - In the case of Outputs or I/Os, AF is selected explicitly by software. Example 1: ADC trigger digital input AF: EXTRG, Port: P4.7, Port Style: Standard I/O. Write the port configuration bits (for TTL level): P4C2.7=1 P4C1.7=0 P4C0.7=1 Enable the ADC trigger by software as described in the ADC chapter. Example 2: PWM 0 output AF: PWM0, Port: P4.0 Write the port configuration bits (for output pushpull): P4C2.0=0 P4C1.0=1 P4C0.0=1 Example 3: ADC AIN1 analog input AF: AIN1, Port : P2.1, Port style: does not apply to analog inputs Write the port configuration bits: P2C2.1=1 P2C1.1=1 P2C0.1=1
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U1 ADDR15 ADDR12 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DAT0 DAT1 DAT2 DAT7 DAT6 DAT5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
C1 CVBS C2 82pF
470nF
C3
82pF ST92R195B C5 22PF
XT1
4MHZ-OSC
C4
C7
1F C6
R3
10k C8
R2 5.6K
82pF C9 R4 5.6K
100nF
S1 4.7NF RST +5V
22PF D1 C10 1N4148 4.7NF
HSYNC VSYNC R G B FB
Figure 3. ST92R195B Required External components
+5V L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MMU0 MMU3 ADDR10 DSN ADDR11 ADDR9 ADDR8 R/WN GNDM VDDM OSCIN OSCOUT ADDR13 ADDR14 MMU1 MMU2 MMU4 MMU5 P3.7/CSO/RESETO P3.6/ASN P3.5 P3.4 P5.1/SDI/SDO/INT1 P5.0/SCK/INT2 10uH DAT4 DAT3 GNDA CVBS1 CVBS2 TEST0 CVBSO TXCF JTRST0 MCFM RESETN PXFM VDDA WSCF WSCR CSYNC/HSYNC VSYNC R G B FB P4.0/PWM0 P4.1/PWM1 P4.2/PWM2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
L2 C12 100nF
10uH 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 QFP80
P2.0/INT7 P2.3/INT6/VSO1 P2.4/NMI P0.2/AIN4 P0.1 P0.0 P4.7/PWM7/INT3 P4.6/PWM6 P4.5/PWM5 VDD GND P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.5/INT4/AIN3/VSO2 P4.4/PWM4 P4.3/PWM3/TSLU/HT
C13 4.7 F
C14
4.7 F +5V
L3
10uH
C15 100nF C16 4.7 F
ST92R195B - GENERAL DESCRIPTION
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ST92R195B - GENERAL DESCRIPTION
1.3 MEMORY MAP No Internal ROM Internal RAM, 1 Kbytes The internal RAM is mapped in MMU segment 20h; from address FC00h to FFFFh. Internal TDSRAM, 8K bytes expandable up to 16K (into segment 22h) The Internal TDSRAM is mapped into theMMU segment 22h. The TDSRAM is a fully static memory. The TDSRAM is an 8K bytes mapped at the address 8000h to 9FFFh.
Figure 4. ST92R195B Memory Map
39FFFFh
External RAM
229FFFh
8 Kbytes TDSRAM
228000h
Reserved
22FFFFh 22C000h 22BFFFh 228000h 227FFFh
PAGE 91 - 16 Kbytes PAGE 90 - 16 Kbytes PAGE 89 - 16 Kbytes PAGE 88 - 16 Kbytes
SEGMENT 22h 64 Kbytes
Reserved
224000h 223FFFh
Reserved
220000h 21FFFFh
SEGMENT 21h 64 Kbytes
Reserved
Internal RAM 1 Kbyte
20FFFFh
210000h 20FFFFh
PAGE 83 - 16 Kbytes
20C000h 20BFFFh
20FC00h
SEGMENT 20h 64 Kbytes
Reserved Reserved
PAGE 82 - 16 Kbytes
208000h 207FFFh
PAGE 81 - 16 Kbytes
204000h 203FFFh
Reserved
200000h
PAGE 80 - 16 Kbytes
01FFFFh
PAGE 7 - 16 Kbytes
01C000h 01BFFFh
SEGMENT 1 64 Kbytes External ROM/EPROM
PAGE 6 - 16 Kbytes
018000h 017FFFh
PAGE 5 - 16 Kbytes
014000h 013FFFh 01000 0h 00FFFFh 00C000h 00BFFFh
PAGE 4 - 16 Kbytes PAGE 3 - 16 Kbytes
SEGMENT 0 64 Kbytes
PAGE 2 - 16 Kbytes
008000h 007FFFh
PAGE 1 - 16 Kbytes
004000h 003FFFh
PAGE 0 - 16 Kbytes
000000h
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ST92R195B - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol V DD V SSA V DDA VI V AI VO TSTG IINJ Supply Voltage Analog Ground Analog Supply Voltage Input Voltage Analog Input Voltage (A/D Converter) Output Voltage Storage Temperature Pin Injected Current Maximum Accumulated Pin Injected Current In Device - 50 to +5 0 mA Parameter Value VSS - 0.3 to V SS + 7.0 VSS - 0.3 to V SS + 0.3 VDD -0.3 to VDD +0.3 VSS - 0.3 to V DD +0.3 VSS - 0.3 to V DD +0.3 VSSA - 0.3 to VDDA +0.3 VSS - 0.3 to V DD + 0.3 - 55 to + 150 - 5 to + 5 Unit V V V V V V C mA
Note: Stress above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD VDDA fOSCE fOSCI Operating Temperature Supply Voltage Analog Supply Voltage (PLL) External Oscillator Frequency Internal Clock Frequency (INTCLK) Parameter Value Min. 0 4.5 4.5 3.3 Max. 70 5.5 5.5 8.7 24 Unit C V V MHz MHz
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ST92R195B - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified)
Symbol VIHCK VILCK VIH VIL VIH VIL VIHRS VILRS VHYRS VIHY VIHVH VILVH VHYHV VOH VOL IWPU ILKIO ILKRS ILKAD ILKOS Parameter Clock in high level Clock in low level Input high level Input low level Input high level Input low level Reset in high level Reset in low level Reset in hysteresis P2.(1:0) input hysteresis HSYNC/VSYNC input high level HSYNC/VSYNC input low level HSYNC/VSYNC input hysteresis Output high level Output low level Weak pull-up current I/O pin input leakage current Reset pin input A/D pin input leakage current OSCIN pin input leakage current Push-pull Ild=-0.8mA Push-pull ld=+1.6mA bidir. state VOL= 3V VOL= 7V 012/18
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS PIN CAPACITANCE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified))
Symbol C IO Parameter Pin Capacitance Digital Input/Output Conditions Value min max 10 Unit pF
CURRENT CONSUMPTION (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified) Symbol IDD1 IDDA1 IDD2 IDDA2 Parameter Run Mode Current Run Mode Analog Current (pin VDDA ) HALT Mode Current HALT Mode Analog Current (pin VDDA ) Condition s notes 1,2; all On Timing Controller On notes 1,4 notes 1,4 Value min typ. 70 35 10 40 max 100 50 100 100 Unit mA mA A A
Notes: 1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor. The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode. 2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock. All peripherals working including Display. 3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock. The TDSRAM interface and the Slicers are working; the Display controller is not working. 4. VSYNC and HSYNC tied to VSS. External CLOCK pin (OSCIN) is held low. All peripherals are disabled.
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode) (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified))
Symbol TwLR TwHR Parameter Low level pulse width High level pulse width Condition s INTCLK=24 MHz. TpC+12 TpC+12 Value min 95 95 max ns ns Unit
TpC is the INTCLK clock period.
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ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont'd) EXTERNAL MEMORY INTERFACE TIMING TABLE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified))
Symbol TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) ThDS(AS) TsRW(AS) TdDSR(RW) TdDW(DSW) ThDS(DW) TdA(DR) Parameter DSN low level pulse width (read) DSN low level pulse width (write) DSN to data valid delay Data to DSN hold time DSN to address active delay DSN to ASN delay R/WN setup time before ASN DSN to R/WN and address not valid delay Write data valid to DSN delay (write) Data hold time after DSN (write) Address valid to data valid delay (read) Value typ TpC*(1/2+WDS)-6 TpC*(1/2+WDS)-6 TpC*(1/2+WDS)-16 0 TpC/2 TpC/2 + 6 TpC*(1/2 + WAS) - 8 TpC/2 0 TpC/2 TpC*(3/2+WDS+WAS)-14 max ns ns ns ns ns ns ns ns ns ns ns Unit
TpC is the INTCLK clock period.
SPI TIMING TABLE (VDD= 5V +/-10%; TA = 0 to 70C; Cload= 50pF)
Symbol TsDI ThDI TdOV ThDO TwSKL TwSKH Parameter Input Data Set-up Time Input Data Hold Time SCK to Output Data Valid Output Data Hold Time SCK Low Pulse Width SCK High Pulse Width tbd tbd tbd (1) OSCIN/2 as internal Clock Conditi on Value min tbd 1INTCLK +100ns tbd max Unit ns ns ns ns ns ns
(1) TpC is the OSCIN clock period; TpMC is the "Main Clock Frequency" period.
SKEW CORRECTOR TIMING TABLE (VDD= 5V +/-10%, TA = 0 to 70C, unless otherwise specified)
Symbol Tjskw Parameter Jitter on RGB output Conditions 36 MHz Skew corrector clock frequency max Value 5* Unit ns
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope of 100 fields
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ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont'd) OSD DAC CHARACTERISTICS (VDD= 5V +/-10%, TA = 0 to 70C, unless otherwise specified).
Symbol Parameter Output impedance: FB,R,G,B Output voltage: FB,R,G,B code= 111 code= 011 code= 000 FB= 1 FB= 0 Global voltage accuracy 2.4 0 Cload= 20pF RL = 100K 1.000 0.459 0.025 3.0 0.025 0.509 0.050 4.0 0.050 +/-5 V V V V V % Conditio ns Value min 300 typical 500 max 700 Unit Ohm
A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified
Symbol Tlow Thigh Text Tstr Tlow Thigh Text Tstr Parameter Pulse Width Pulse Distance Period/fast Mode Start Conversion Delay Core Clock issued by Timing Controller Pulse Width Pulse Distance Period/fast Mode Start Conversion Delay ns ns s ns 78+1 INTCLK 0.5 1.5 OSCIN divide by 2;min/max OSCIN divide by 1; min/max Value min 1.5 INTCLK max Unit ns ns s INTCLK
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ST92R195B - ELECTRICAL CHARACTERISTICS
A/D CONVERTER. ANALOG PARAMETERS TABLE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified)
Parameter Analog Input Range Conversion Time Fast/Slow Sample Time Fast/Slow Power-up Time Resolution Differential Non Linearity Integral Non Linearity Absolute Accuracy Input Resistance Hold Capacitance
Notes: (*) (**) (1) (2) (3) (4)
Value typ (*) min VSS 78/138 51.5/87.5 60 8 1.5 2 2 2.5 3 3 1.5 1.92 max V DD
Unit (**) V INTCLK INTCLK s bits LSBs LSBs LSBs Kohm pF
Note
(1,2) (1)
(4) (4) (4) (3)
The values are expected at 25 Celsius degrees with VDD= 5V 'LSBs' , as used here, as a value of VDD/256 @ 24 MHz external clock including Sample time it must be considered as the on-chip series resistance before the sampling capacitor DNL ERROR= max {[V(i) -V(i-1)] / LSB-1} INL ERROR= max {[V(i) -V(0)] / LSB-i} ABSOLUTE ACCURACY= overall max conversion error
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ST92R195B - GENERAL INFORMATION
3 GENERAL INFORMATION
3.1 PACKAGE MECHANICAL DATA Figure 5. 80-Pin Plastic Quad Flat Package
0.10mm .004 seating plane mm Min 0.25 0.30 0.13 Typ Max 3.40 0.010 0.45 0.012 0.23 0.005 0.018 0.009 Min inches Typ Max 0.134
Dim A A1 A2 B C D D1 D3 E E1 E3 e K L L1 N
2.55 2.80 3.05 0.100 0.110 0.120
22.95 23.20 23.45 0.904 0.913 0.923 19.90 20.00 20.10 0.783 0.787 0.791 18.40 0.724 16.95 17.20 17.45 0.667 0.677 0.687 13.90 14.00 14.10 0.547 0.551 0.555 12.00 0.80 0 1.60 80 ND 24 7 0.063 NE 16 0.472 0.031
0.65 0.80 0.95 0.026 0.031 0.037 Number of Pins
PQFP080
3.2 ORDERING INFORMATION
Sales Type ST92R195B9Q1 OSD 50/60 or 100/120 Hz Temperature Range 0-70C Package PQFP80
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ST92R195B - GENERAL INFORMATION
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2000 STMicroelectronics - All Rights Reserved. Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com
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